The present invention relates to a memory comprising an array of memory cells each storing a bit to be read, with read means which are responsive to a read control signal, an array of bit lines each provided with precharging means for being precharged in response to a precharge control signal and, located at tee end of each bit line, a read buffer amplifier controllable by a transmission transistor for producing on an output line, an amplified stable signal which is representative of the value of a bit read.
This type of memory is well known and is frequently used in the electronics and information processing industries.
A known example of such a memory is disclosed in the publication "IEEE International Solid-State Circuits Conference, Feb. 12th 1982, IEEE, New York (US) S. Konishi--A 64 Kb CMOS--RAM, pages 258-259". Another known example is shown in FIG. 2 of U.S. Pat. No. 4,003,034.
Substantially all types of memories, random-access memories, read-only memories etc . . . , are realized in the form of a matrix of bit cells, each cell being positioned at the intersection of a column and a row; during a read operation one signal cell of each row is read and the information is transmitted to a bit line which is used in common by all the cells of the same row; the actual read arrangement, here denoted read sense amplifier, is arranged at the end of each bit line; the present invention relates more specifically to the read sense amplifier.
In prior art memories, more specifically those implemented in MOS technology, the sense amplifier with buffer generally comprises an amplifier ("sense amplifier"), a transmission transistor ("passing transistor") responsive to the read control signal, and a buffer ("latch"); it consequently includes at least eight transistors; the present invention has for its object to reduce this number of transistors.